Matrix memory system



MATRIX MEMORY SYSTEM Jean Francois Marchand, Eindhoven, Netherlands, as-

signor to North American Philips Company, Inc., New York, N .Y., acorporation of Delaware Filed Oct. 9, 1958, Ser. No. 766,311 7 Claimspriority, application Netherlands Oct. 17, 1957 6 Claims. (Cl. 340-174This invention relates to a matrix memory system comprising a pluralityof memory elements each of which is made of magnetic material having ahigh remaneuce. In known systems of this kind the memory elementsareeachmagnetically coupled to one of a first group of conductors and toone of a second group of conductors, means being provided 'for changingthe magnetic state of a certain memory element by variation of theelectrical state of the group conductors coupled to this memory core. Inthese known systems apulse is supplied simultaneously to both conductorscoupled to this core so that the double'pulse causes the; core to changeits remanence state; the cores which are coupled to only onecurrent-carrying conductor must not be influenced by this current. Ithas, however, been found that in practice the last-mentioned cores may.nevertheless be influenced to a certain degree thus interfering with thememory operation.

The present invention obviates this disadvantage. In the matrix memorysystem in accordance with the invention the undesirable reaction on theelements which are coupled to only one current-carryingconductor isprevented due to the fact that all the conductors are short- 2,979,701Patented Apr. 11, 1 361 Fig. 2 shows an example of a hysteresis loop a,b, c, d, e, f, g, h, i, a, of a" magnetic material which can be used inthe cores K11, K12, and so on. Each core can be either in a state ofpositive magnetic remanence P or in a state of negative remanence N,these states corresponding, for example, to the binary digits 1 and 0.

In the known matrix memory arrangements there are no short-circuitcontacts CH1, CH2, and so on. A certain core, for example K22, can beset to a certain remanencejstate, for example the state P, by applyinga' current pulse J to the horizontal conductor CH2 and to the verticalconductor CV2 simultaneously. Thusthe double pulse 2] 'is applied to thecore K22. If this core was in the state N, the branch a, b, c, d, e, f,of the hysteresis loop is traversed so that the core is set to the stateP. The cores K21, K23, K12 and K32 have only the single pulse I appliedto them in order that their magnetic states are not changed under thecontrol of the single pulse J. This means that the saturation regiona'bof the magnetization 'curve must be comparatively large and moreparticularly that the current strength JK, which corresponds to the kneeb of the magnetization curve, must exceedthe pulse strength 1.Consequently comparatively'exacting requirements must be satisfied withrespect tothe shape of the hysteresis loop ,so that the material iscomparatively expensive.

circuited in themselves with the exception of the two conductors whichare coupled to the memory elements the magnetic state of which is to bechanged. v

The invention will now be described more fully with reference to theaccompanying drawings, in which:

Fig. 1 shows a system in accordancewith theinvention, I Fig. 2 shows ahysteresis loop of a magneticmaterial which can be used in this system,and p Fig.3 shows a modified embodiment of a system in accordance withthe invention. e i i Fig. 1 shows diagrammatically a' number of memoryelements K11, K12, K13 K32, K33 made of a mag netic material having arectangularhysteresis loop and arranged according to a matrix. All coresof one horizontal row are coupled to one horizontal conductorHl, H2 andH3 respectively, and all cores of one vertical column are coupled to onevertical conductorjVl, V2

and V3, respectively. The ends of the conductors are for example, betransformers the primary windings of which are constituted bytheconductors H1, H2 and, so on,,a secondary winding of each transformer.Ibeing short-circuited, forexample, through a transistor so that theinternal impedances of-the transistors are stepped down towards theconductors The short-circuit can 'be The hysteresis loop shOWn in Fig. 2does not satisfy this requirement, for in this loop the pulse strength.I exceedsthe'current IK corresponding to the knee b in the hysteresisloop. It should be noted that in practice the knees b' and g generallyare lesssharply bent than is shown in the drawing.

Thecores K21, K23, K12 and K32, to which only the single pulse Iisapplied, will be. driven only under the control of this pulse and withthe shape shown of the hysteresis curve along the branch ab-cj;consequently, on termination of the pulse, these cores do not return tothe zero state N but will be set to the state j. In other words, thezero state is disturbed and thisis undesirable. 2

If similarly in the systemshownin Fig. lthe binary digit 1 is to bestored'in the core K22, the switch contacts CHZ'and CV2 are switchedover to the work position so that the conductors H2 and V2 are connectedto the pulse source JB. As a; result the core K22, similarly to what hasbeen described hereinbefore, under the control of the double pulse.2Jtraverses the branch a- -b cde-fof the hysteresis loop and passes tostate P. The cores K21, K23, K12fand K32 likewise have a current pulse]applied to them through the conductors H2 and V2. In the system shown inFig. 1, however, the

conductors H1, H3, V1 and V3 now are short-circuited in themselvesthrough thecontacts cHl, CH3,'CV1-and produced in the short-circuitedconductor V1, this current having a' direction such as to oppose thechange in the magnetization,its strength with sufiicientlylowimpedanceat theshort-circuit being about equal to the current J- JKso-that. the core K21 is not driven beyond the kneeb of themagnetization curve shown in Fig. 2and on termination of the pulsereturns to the state N. Thus the zero state N is not disturbed; ,To theshort circuited conductor V1 there are coupled, in addition to the coreK21, the cores K11- and K31. Since these cores are driven by the.short-circuit currents in the conductors coupled to them into thesaturation state ab only, thepresence of these cores causes only a very'slight1in-- v crease in the impedanceof thetshort-circuit of the con-1eliminated by rendering the transistors non-conductive. ductor V1.

Experiments have shown that the number of cores associated with oneconductor can be high without any difficulty, for example may be 100 ormore, provided that the spacings between the cores are not too large,for example /2 cm. or less. An advantage of the system described ascompared with the known systems consists in that with the use of thesame magnetic material the strength of the applied pulses can be greaterso that the speed at which the system can be operated can be higher thanin the known systems. The abrupt changes of the magnetization states ina core have a cer' tain inertia, the speed of these changes beingproportional not to the strength of the pulse but to the pulse strengthless a constant value corresponding to the coercive force. This meansthat the rate of change increases with the pulse strength notproportionally but at a higher rate.

Reading-out of the information from a certain core, for example K22, cantake place similarly. In this event, the conductors H2 and V2 areconnected to a source the polarity of which is opposite to that of thesource used in storing. When the core K22 is in the state 1, this corewill pass to the state so that a reaction pulse can be taken from anauxiliary conductor coupled to all cores (not shown in the drawing). Achange of the magnetic state of the cores K21, K23, K12 and K32 is inthis event prevented by the occurrence of reaction currents in theremaining short-circuited conductors similarly to what occurs in theprocess of storing information.

In the system described, the information is stored or read out bysimultaneously applying a pulse to both conductors coupled to a certaincore. However, it has been found that alternatively the remanence stateof a cer: tain core, for example K22, can be changed to the oppositestate by applying a pulse to only one of the conductors H2 and V2, forexample to the conductor H2, and eliminating the short-circuit of theother conductor V2. Consequently the conductor V2 is not connected to apulse source and the pulse source to be connected to the conductor H2must have a strength which is double that used in the preceding case.Although now the strength of the current passing through the conductorH2 is sufiicient to cause the cores K21 and K32 also to pass to anotherremanence state, this is prevented by the reaction current which isproduced in the short-circuitecl conductors V1 and V3. This measureprovides simplified switching since the control pulse need be suppliedto one of the control conductors only, so that the pulses to be appliedto the various conductors need not be synchronized, as is the case inthe known systems.

Fig. 3 shows a modified embodiment .of the system in accordance with theinvention, in which control pulses no longer have to be applied toindividual control conductors, as in the case in the known systems, butonly to a single control point SB common to all cores. Here also thecores of one horizontal row are coupled to one horizontal conductor H1H4 respectively and the cores of one vertical column are coupled to onevertical conductor V1 .V4 respectively. Switching contacts in the formof transformers CH1 CH4 and CV1 CV4 respectively, the primary windingsof which are constituted by the conductors H1 H4 and V1 V4 respectively,are connected in series with the conductors. The ends of the secondarywindings are connected to the emitters and collectors of transistors,for example TH3 and TV4, as is shown for the transformers CH3 and CV4. Atapping on each secondary winding is earthed while the bases of thetransistors are connected to a negative voltage supply throughresistances, for example RH3 and RV4. Normally the two blocking layersof the transistors are conductive, a current flowing from the emitter tothe base and from the collector to the base. The internal impedance ofthe transistors when conducting is comparatively low and of the order ofmagnitude of a few ohms. Because of the transformers CH1 CH4, CV1 CV4these resistances are materially stepped down towards the conductors H1H4 and V1 V4 so that the impedance of the primary windings is very lowand forms a short-circuit. Furthermore all cores are coupled to thecontrol conductors SH and SV each of which is connected at one end tothe control terminal SB and at the other to earth. The controlconductors are threaded through the various cores so that the currentsin these conductors act in support of each other magnetically in thevarious cores. The conductor SH extends in parts parallel to allhorizontal conductors H1, H2, H3 and H4 and is arranged in closestproximity to these conductors so that there is strong magnetic couplingwith those conductors; hence, when an alternating current fiows in theconductors SH, there is induced in a short-circuited conductor H1 H4 acurrent the direction of which is opposite to that of the current in theconductor SH, the current amplitudes being substantially equal. Theconductor SV is arranged similarly so as to extend parallel to thevertical conductors V1 V4 and tightly coupled therewith magnetically sothat an alternating current in the conductor SV produces an oppositereaction current in each vertical conductor V1 .V4. If required, thiseltect can be further enhanced by coupling the control conductor to theshort-circuit conductors by means of a separate transformer auxiliarycoupling, for example by means of an auxiliary core of high-frequencymagnetic material, such as the core HK shown in broken lines. Ifrequired, the conductors SV and SH can be connected in series. Thus,when the control terminal S3 is connected to a pulse source, thecurrents in the control conductors SH and SV are substantially balancedby the currents of opposite direction in the short-circuit conductors,so that these currents cannot exert any magnetic action upon the memorycores.

Storing of information in a certain core, for example K34, is effectedby applying a positive potential to terminals BH3 and BV4 so that thetransistors TH3 and TV4 are cut off, the short-circuit of the conductorsH3 and V4 thus being eliminated, A current pulse of suitable polaritywhich is applied through the control terminal SB to the conductors SVand SH, causes the core K34 to pass to the desired remanence state. Theother cores are not influenced by this pulse since each of these coresremains coupled to at least one short-circuited conductor so that anychange in the state of magnetization is counteracted by the reactioncurrent in these shortcircuited conductors. Reading-out the informationfrom a certain core can be effected similarly by applying in the mannerdescribed a pulse of opposite polarity to this core so that a reactionpulse can be taken from a readout conductor coupled to all cores (notshown). This method has a disadvantage in that, in the process ofreading-out, the information is destroyed and, if required, must bestored again. However, the information can alternatively be read out bymeans of an alternating current the amplitude of which is so small thatthe remanence state of the core concerned is not changed. If, forcxample, the information from the core K34 must be read out, theshort-circuit of the conductors H3 and V4 is eliminated by cutting-offthe transistors TH3 and TV4 while at the same time an alternatingcurrent is supplied to the control conductors SH and SV through theterminal SB.

If the amplitude of this alternating current only slightly exceeds thevalue JK which corresponds to the knee b of the hysteresis loop of Fig.2, the magnetization reversibly traverses a small hysteresis loop in theproximity of the instantaneous remanence state N or P, so that, when thealternating current is switched off, the core returns to this remanencestate. Since the hysteresis loop is differently curved in the proximityof the two remanence points N and P, that is to say, downwards in theproximity of the remanence point P and upwards at the remanence point N,an asymmetrical reaction current is produced in a read-out conductorcoupled to all cores (not shown).

If the core K34 is in the state N, the positive phase of this reactioncurrent, for example, exceeds the negative phase while conversely, ifthe core K34 should be in the state P, the positive phase of thereaction current would be smaller than the negative phase. By, comparingthe two phases of the reaction currents the remanence state of the corecan be ascertained. It has been found that the amplitude of the read-outalternating current at the terminal SB can advantageously be made muchgreater than the value IK provided that the frequency of thisalternating current is made sufficiently high, for example higher than 1mc./s., in which event the process remains reversible, the value of thereaction current, however, being greater than with a comparatively smallvalue of the read-out alternating current.

What is claimed is:

1. A matrix memory system comprising a plurality of memory elementscomposed of magnetic material having a substantially rectangularhysteresis loop, first and second groups of conductors, each elementbeing magnetically coupled to one conductor of the first group and oneconductor of the second group, means for varying the electric state ofthe conductor of each group coupled to a desiredelement, and means forshort-circuiting each of the remainder of the conductors of the matrix,whereby undesirable remanences in the remaining elements of the matrixare eliminated.

2. A memory system as claimed in claim 1, wherein each element is anannular magnetic core.

3. A memory system as claimed in claim 1, wherein said short-circuitingmeans comprises a highly conductive frame surrounding said matrix, bothends of each conductor being connected to said frame.

4. A matrix memory system as claimed in claim 1, wherein said varyingmeans comprises at least one control conductor magnetically coupled toeach memory element and also arranged in close magnetic couplingproximity to all conductors of each group, whereby the current in thecontrol conductor produces a reaction current in each short-circuitedconductor thus cancelling the elfect of the control current therein.

5. A matrix memory system comprising a plurality of annular magneticmemory cores composed of magnetic material having a substantiallyrectangular hysteresis loop, first and second groups of conductors, eachcore being magnetically coupled to one conductor of the first group andone conductor of the second group, means for applying a writing pulse tothe conductor of each group coupled to a desired element, each pulsehaving a magnitude one-halfof that'necessary to change-over a core fromone saturation condition to another, and means for short-circuiting eachof the remainder of the conductors of the matrix, whereby undesirableremanences in the remaining cores of the matrix areeliminated.

6. A matrix memory system comprising a plurality of annular magneticmemory cores composed of magnetic material having a substantiallyrectangular hysteresis loop, first and second groups of conductors, eachcore being magnetically coupled to one conductor of the first group andone conductor of the second group, means for short-circuiting each ofthe conductors of the matrix, means for applying a writing pulse to aselected conductor of one group, means for eliminating the short-circuitof a selected conductor of the other group, the magnitude of saidwriting pulse being suflicient to change-over a core from one saturationcondition to another, whereby undesirable remanences in all cores otherthan the core coupled to said selected conductors are eliminated.

References Cited in the tile of this patent UNITED STATES PATENTS

